Summary

The Arquimea MEDiTC IP core is an IP core for low latency error detection and diagnosis through TRACE interface of ARM uP and SEU/SEFI mitigations. The IP core consists of a program checker for range and watchdog, and data checker for control and consistency. The MEDiTC mitigates the Single Event Effects in ARM uP by offering a non-intrusive solution. The IP core has achieved TRL4 currently and is expected to achieve TRL5/6 in 2022.

Applications

Typical applications include:

  • OBC
  • Artificial Intelligence
  • Signal treatment:
    • Data acquisition
    • Hyperspectral imaging
    • Image & SAR processing
    • Data filtering (FIR)
    • Data processing (FFT)
    • Data compression (CCSDS)

Key features

  • Suitable for ARM microP
  • Online operation in real-time
  • Ultra-low latency error detection
  • Comprehensive error diagnosis
  • Reduced footprint
  • User-configurable
  • Multicore support
  • Easily Configurable, with multicore uP

Testing & qualification

Arquimea's Quality Management System meets the requirements of UNE-EN 9100:2018 Aerospace Series and has been audited and certified by the Spanish Association for Standardization and Certification, AENOR.

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Last updated: 2022-02-11

MEDiTC IP

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