ABACUS 2017 is an OBC (On-Board Computer) subsystem with a general-purpose hardware platform, suited for a wide range of satellite and CubeSat missions. It is designed to be flexible and scalable in terms of processing power, with the goal of maintaining a very low power consumption. The presence of a MSP430 (EP series) microcontroller and a Spartan-3E FPGA, organized in two independent but cooperative cores, provides the system with hardware redundancy and common mode fault tolerance. The two cores offer many modalities to be implemented (e.g. Master/Slave or multi-Master) and the FPGA offers all the advantages of the RTL coding, for implementing specific tasks (e.g. attitude control) or generic systems also with IP cores of third parts. With the FPGA, high reliability may be achieved using TMR (triple modular redundancy) configuration codes. Several embedded sensors provide health monitoring and attitude control data. The system design offers the possibility to reconfigure the FPGA code and the MCU firmware in flight. ABACUS is compatible with FreeRTOS Real-time Operating System, as the MCU used in ABACUS has been already successfully employed in FreeRTOS ports.

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Last updated: 2020-12-11



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