No image available, showing a placeholder.

Key highlights

The rad-tolerant logic family includes options for NAND gate, inverter, buffer, flip-flop, comparator. The parts feature plastic packaging, wide temperature range, and SEE immunity to LET of 37 to 83 MeV-cm2/mg. See performance specifications at https://www.zerogdevices.com/rt-logic.

Key features

  • ZG54HC132: Schmitt-Trigger NAND gate with 4 channels and 2 inputs. The part is qualified to AEC-Q100 standards. SEL immune up to LET of 37 MeV-cm2/mg. The part is available in a SOIC-14 package.
  • ZG54CD00: Dual channel, 4-input NAND gate. SEL immune up to LET of 58 MeV-cm2/mg. The part is available in a SOIC-14 package.
  • ZG54HC14: 6 channel high-speed CMOS inverter with Schmitt-Trigger inputs. The part is qualified to AEC-Q100 standards. We have performed radiation qualification for SEL immunity up to LET of 60 MeV-cm2/mg. The part is available in a SOIC-14 package.
  • ZG54LVC14: 6-channel inverter with Schmitt trigger inputs. SEL immune up to LET of 60 MeV-cm2/mg. The part is available in a SOIC-14 package.
  • ZG54HC244: Buffer with 3-state outputs, 8 channels. The part is qualified to AEC-Q100 standards. SEL immune up to LET of 83 MeV-cm2/mg. The part is available in a SOIC-20 package.
  • ZG54HCT244: Buffer with TTL-compatible CMOS inputs, 3-state outputs, and 8 channels. The part is qualified to AEC-Q100 standards. SEL immune up to LET of 83 MeV-cm2/mg. The part is available in a TSSOP-20 package.
  • ZG54LVC244: Buffer with 8 channel bus, 3 state output. The part is qualified to AEC-Q100 standards. SEL immune up to LET of 60 MeV-cm2/mg. The part is available in a SSOP-20 package.
  • ZG54HC74: Dual, D-type Flip-Flop, positive-edge-triggered with clear and preset. The part is qualified to AEC-Q100 standards. SEL immune up to LET of 58 MeV-cm2/mg. The part is available in a SOIC-14 package.
  •  ZG54HC688: 8-bit digital comparator. SEL immune up to LET of 83 MeV-cm2/mg. The part is available in a SOIC-20 package.

Testing & qualification

  • JEDEC, "Test procedure for the management of single-event effects in semiconductor devices from heavy ion irradiation," JESD57A, Nov 2017
  • ESA "Single Event Effects Test Method and Guidelines," ESCC No. 25100, Oct 2014.

Disclaimer: satsearch is not responsible for any mistakes on this page, although we do our best to ensure correctness. Please report any mistakes to us.

Last updated: 2026-07-24

Radiation tolerant logic devices

No image available, showing a placeholder.

Downloads

Export

  • Click here to add the Zero-G Radiation Assurance - Radiation tolerant logic devices to the Valispace engineering tool from satsearch
  • Click here to add the Zero-G Radiation Assurance - Radiation tolerant logic devices to Lynapse Studio by Spacebackend
  • Click here to add the Zero-G Radiation Assurance - Radiation tolerant logic devices to 360 by IENAI

from our blog

Go to blog

Microsatellite and CubeSat platforms on the global market

Spotlight: Space Enhanced Plastic products for NewSpace - with Texas Instruments

Spotlight: Acktar - coatings for space systems